1. Field of the invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for use in an in-plane switching mode liquid crystal display device (IPS-LCD).
2. Description of Related Art
In general, liquid crystal display device (LCD) includes a display panel which have upper and lower substrates attached to each other with a liquid crystal layer interposed between the upper and lower substrates. These upper and lower substrates are respectively referred to as color filter and array substrates. Further, the display panel includes retardation films and polarizers on its exterior surfaces. Because the LCD device is selectively comprised of the above-mentioned elements, it converts the state of incident light and changes light refractive index in order to have great brightness and high contrast ratio.
Although the liquid crystal molecules in the liquid crystal layer are usually twisted nematic liquid crystals, use of the twisted nematic liquid crystal layer in the large-sized display panel is limited because of unstable transmittance of the twisted nematic liquid crystal layer, which depends on viewing angle. Moreover, the light transmittance varies depending on vertical viewing angle and is asymmetrically distributed compared to symmetric distribution in horizontal viewing angle. Thus, a range of reverse-image occurs when the viewing angle is vertically slanted. Thus, the viewing angle becomes narrow.
In order to solve the problem of the narrow viewing angle, in-plane switching liquid crystal display (IPS-LCD) devices have been proposed. IPS-LCD devices typically include a lower substrate where a pixel electrode and a common electrode are disposed, an upper substrate having no electrode, and a liquid crystal interposed between the upper and lower substrates. In this typical structure, the liquid crystal molecules are driven by a horizontal electric field. Contrast ratio is increased and color-shift is prevented. Thus, the characteristics of viewing angle are improved.
FIG. 1 is a plan view illustrating one pixel of an array substrate of a conventional in-plane switching mode liquid crystal display (IPS-LCD) device. As shown, a plurality of gate lines 14 are transversely disposed on a substrate (see reference element 11 of FIG. 2A). A common line 12 is spaced apart from and disposed parallel with the gate lines 14. A plurality of data lines 13 that are spaced apart from each other are disposed across and perpendicular to the gate and the common lines 14 and 12. Each pair of gate and data lines 14 and 13 defines a pixel area “P”.
Near the crossing of the gate and data lines 14 and 13, a switching device, i.e., a thin film transistor that is indicated by a portion “T”, is positioned. As shown in an enlarged view of a portion “T”, gate and source electrodes 21 and 17 are positioned and electrically connected with the gate and data lines 14 and 13, respectively. A drain electrode 19 is spaced apart from the source electrode 17 and overlaps one end of the gate electrode 21. The source electrode 17 also overlaps the other end of the gate electrode 21. An active layer 15 is located over the gate electrode 21 and under the source and drain electrodes 17 and 19. A first pixel-connecting line 25a, which is connected with one end of each respective pixel electrode 25, electrically contacts the drain electrode 19 through a drain contact hole 35, and is disposed parallel with the gate line 14.
Still referring to FIG. 1, a plurality of common electrodes 23 are disposed parallel with the data line 13 and spaced apart from each other. One end of each common electrode 23 is electrically connected to the common line 12, and the other end of each common electrode 23 contacts a common-connecting line 23a. A plurality of pixel electrodes 25 are disposed perpendicular to the first pixel-connecting line 25a, and communicate with the first pixel-connecting line 25a. The pixel electrodes 25 are spaced apart from each other and parallel with the adjacent common electrodes 23. Moreover, each pixel electrode 25 corresponds to an adjacent common electrode 23. The other ends of the pixel electrodes 25 are connected with a second pixel-connecting line 25b that is over the common line 12. The second pixel-connecting line 25b overlaps a portion of the common line 12 such that a storage capacitor “C” is comprised of the common line 12, the second pixel-connecting line 25b and an interposed dielectric layer. Although FIG. 1 shows four common electrodes and three pixel electrodes, the number of the common and pixel electrodes depends on spaces between electrodes.
Still referring to FIG. 1, the gate and common lines 14 and 12 have a double-layer structure, respectively, in order to prevent signal delay of these lines. Moreover, the gate electrode 21 is also a double layer. Namely, the gate line 14 is comprised of first and second layers 14a and 14b and the common line 12 is also comprised of first and second layers 12a and 12b. The first layers 14a and 12a are usually a substance having low electrical resistance, such as Aluminum (Al). However, Aluminum is low in hardness and chemical resistance. So open-circuits and oxidation easily occur during an etching process. To overcome this problem, a second layer is formed on the first layer usually of a substance having high hardness and good chemical resistance, such as Molybdenum (Mo) or Chrome (Cr). Moreover, the first and second pixel-connecting lines 25a and 25b, and the pixel electrodes 25 are a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Each pixel electrode 25 is positioned between the common electrodes 23 so that each pixel and common electrodes 25 and 23 is arranged one after the other. The data line 13 and the source and drain electrodes 17 and 19 are made of the metallic material selected from a group consisting of chromium (Cr), aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), tantalum (Ta), tungsten (W), and antimony (Sb), and the like.
However, such a structure has a problem. During a patterning process of the data line 13, the remains of the above-mentioned substance (Cr, Mo, Ta, W or the like) are left in step portions “A” around the common line 12. These remains are not completely removed during the patterning process of the data line 13, and exist in the capacitor “C” such that the short-circuit occurs between the data line 13 and the storage capacitor “C”.
FIGS. 2A to 2D are cross-sectional views taken alone lines II—II and III—III of FIG. 1 and illustrate fabricating processes for the array substrate.
Referring to FIG. 2A, the first gate line 14a (see FIG. 1) is formed on the substrate 11 by depositing and patterning a conductive metal having low electrical resistance, such as Aluminum (Al). The first gate electrode 21a that is extended from the first gate line is formed with the first gate line on the substrate 11. Simultaneously, the first common line 12a is formed when the first gate line and the first gate electrode are formed. Thereafter, the second gate line 14b (see FIG. 1), the second common line 12b and the second gate electrode 21b are formed on the respective first layers of these components by depositing and patterning the conductive metal having the high hardness and chemical resistance, such as Cr, Mo, or the like. Namely, the second gate line 14b (see FIG. 1) is formed to cover the first gate line 14a, the second common line 12b is formed to cover the first common line 12a, and the second gate electrode 21b is formed to cover the first gate electrode 21a. Thus, the double-layered gate line 14 (see FIG. 1) is formed on the substrate 11. The double-layered gate electrode 21 that is extended from the gate line 14 is also formed on the substrate 11. The double-layered common line 12 that is parallel with the gate line 14 is formed.
Still referring to FIG. 2A, when forming the second common line 12b, a plurality of common electrodes 23 and the common-connecting line 23a (see FIG. 1) are formed on the substrate 11. So the common electrodes 23 are extended from the common line 12 and electrically connect the common-connecting line 23a (see FIG. 1) to the double-layered common line 12.
Referring now to FIG. 2B, a gate insulation layer 27 is formed on entire surface of the substrate 11 to cover the conductive layers formed previously. The gate insulation layer 27 is an inorganic substance, such as silicon nitride (SiNx) or silicon oxide (SiO2), or an organic substance, such as BCB (benzocyclobutene) or acryl-based resin. Subsequently, the active layer 15 is formed on the gate insulation layer 27, particularly over the gate electrode 21. After that, ohmic contact layer 16 is formed on the active layer 15, and thus the ohmic contact layer 16 is interposed between the active layer 15 and the source and drain electrodes that are formed in a later step. The active layer 15 is formed by depositing and patterning an amorphous silicon layer (a-Si), while the ohmic contact layer 16 is formed by depositing and patterning a doped amorphous silicon layer (n+ a-Si).
Referring now to FIG. 2C, the source and drain electrodes 17 and 19 are formed on the ohmic contact layer 16, and are made of the conductive metallic material selected from a group consisting of chromium (Cr), aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), tantalum (Ta), tungsten (W), and antimony (Sb), and the like. By depositing and patterning these materials, not only the source and drain electrodes 17 and 19 but also the data line 13 is formed on the gate insulation layer 27 such that the source electrode 17 is extended from the data line 13. The source and drain electrodes 17 and 19 are spaced apart from each other and respectively overlap opposite ends of the gate electrode 21. Moreover, a portion of the ohmic contact layer 16 between the source and drain electrodes 17 and 19 is eliminated to form a channel region. At this time when forming the data line 13 and the source and drain electrodes 17 and 19, the residues of the material forming the data line 13 and the source and drain electrodes 17 and 18 are left in a ridge, or step portion, of the portion “A”. The step is caused by the formation of the two layers 12a and 12b of the common line 12. After forming the data line 13 and the source and drain electrodes 17 and 19, these residues spread over a interval between the storage capacitor “C” (see FIG. 1) and the data line 13, and thus result in the short-circuit between them. A passivation layer 33 is then formed on and over the above-mentioned intermediates by depositing an organic or inorganic insulating material. After that, a drain contact hole 35 that exposes a portion of the drain electrode 19 is formed by patterning the passivation layer 33.
Now, referring to FIG. 2D, on the passivation layer 33 having the drain contact hole 35, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and then patterned to form the pixel electrodes 25 and the first and second pixel-connecting lines 25a and 25b. Thus, the first pixel-connecting line 25a contacts the portion of the drain electrode 19 through the drain contact hole 35, and the second pixel-connecting line 25b overlaps the portion of the common line 12, thus the second pixel-connecting line 25b and the common line 12 comprise the storage capacitor “C”.
According to aforementioned structure of the array substrate for use in the IPS-LCD device, the residual substances remaining the portions either side of the storage capacitor connect the data line to the storage capacitor. Thus, the residues cause the short in the storage capacitor. The short results in discharge of the electric charge stored in the storage capacitor through the data line. Moreover, the residues deteriorate the driving characteristics of the liquid crystals and bring about the point defect in the display panel.